A Calibrated Cost and Yield Analysis Model for Gallium Arsenide Monolithic Microwave Integrated Circuits

Period of Performance: 01/01/1987 - 12/31/1987

$499K

Phase 2 SBIR

Recipient Firm

Anadigics, Inc.
35 Technology Dr
Warren, NJ 07060
Principal Investigator

Abstract

TO OBTAIN AN ACCURATE COST AND YIELD FIGURES FOR A MONOLITHIC SUBSYSTEM IT BECOMES NECESSARY TO LINK THE DESIGN, PROCESSING AND FABRICATION, TESTING AND ASSEMBLY ACTIVITIES TO A COMMON MONITORING ACTIVITY. SUCH AN ACTIVITY WOULD DIRECT TOWARDS OBTAINING DATA FROM PROCESS, FABRICATION AND TESTING AND MAKE SUBSTANTIAL USE OF INPROCESS TESTING TO SCREEN OUT CIRCUITS AT AN EARLY STAGE. MMIC YIELD IS THE SIGNIFICANT FACTOR IN DETERMINING BOTH CHIP COST AND LEVEL OF INTEGRATION. IN ORDER TO MAXIMIZE YIELD IT IS NECESSARY TO ESTABLISH A CONSISTENT, REPRODUCIBLE PROCESS CONTROL, COUPLED WITH CREATIVE CIRCUIT DESIGN TECHNIQUES USED TO CREATE CHIP SETS WHICH ARE TOLERANT TO PROCESS VARIATION. A LARGE PROPORTION OF THE FINAL COST IS ALSO RELATED TO FINAL ASSEMBLY AND TESTING. THE PHASE II WORK WILL DEVELOP A CALIBRATED MODEL FOR COST AND YIELD ANALYSIS AND WILL INCORPORATE THE AVERAGE COMPONENT YIELD FACTORS FOR EACH ACTIVE AND PASSIVE ELEMENT, DETERMINED FROM THE PROCESS. IN ADDITION THE ANALYSIS, AS A SOFTWARE PACKAGE, WILL HAVE FLEXIBILITY SO AS TO LET ANY GALLIUM ARSENIDE FOUNDRY TO CALIBRATE IT TO THEIR PROCESS. THE FINAL SOFTWARE PACKAGE WILL BE MARKETED COMMERCIALLY IN PHASE III.