SBIR Phase I: Integrated Nano-Electro-Mechanical Scanning Probes for Failure Analysis of the 10-Nanometer Node and Beyond

Period of Performance: 01/01/2015 - 12/31/2015


Phase 1 SBIR

Recipient Firm

Xallent LLC
107 Hillcrest Drive
Ithaca, NY 14850
Firm POC, Principal Investigator


This Small Business Innovation Research Phase I project will focus on the development of a multiple integrated tip scanning probe device for use in semiconductor device failure isolation and analysis. The underlying motivating factor stems from a lack of testing equipment with high resolution and sensitivity necessary for identifying faults as the semiconductor industry shrinks feature sizes to 10 nanometers and beyond. Successful development and use of the integrated device will allow engineers to understand the root cause of failure mechanisms of solid state devices at these advanced nodes. The commercial impact of this new capability for failure analysis on next-generation devices will be profound. The miniaturization of semiconductor devices has led to a decrease in the cost per transistor of seven orders of magnitude in the last 40 years, and new process and measurement technologies are needed to continue this trend. The reduction of transistor size enables high performance devices at a lower cost and lower power. The proposed multiple tip technology will enable the development of these advanced-node highly scaled transistors that will form the platform for the next generation of high-performance electronic devices such as personal computers, cell phones, and healthcare equipment. The intellectual merit of this project is the use of monolithically integrated scanning probes to facilitate the extension of semiconductor failure analysis to devices with feature sizes of ten nanometers or less. Crucially, conventional characterization and test methods are increasingly ineffective when applied to structures smaller than 100 nanometers, causing challenges for engineers in research and development, process control and failure analysis. Subtle defects become increasingly prominent drivers of failure as device size and operating margins decrease, e.g., processing anomalies in thin gate oxides, substrate problems related to doping, and line width variations. These issues can occur at length scales invisible to traditional scanning electron microscopy and optical-based tools, requiring novel approaches. The proposed multiple integrated tip devices leverage powerful nano-electro-mechanical capabilities and scale well even below 10 nanometers. In addition, cost effectiveness of the nanofabrication techniques, combined with monolithic integration of sensing structures and tailoring of the tips would enable robust, high-volume testing, a key need for the semiconductor industry. Research objectives include the fabrication of nanoscale multiple integrated tip devices, atomic force imaging of transistors and active electrical characterization of transistors. The anticipated result is accurate electrical characterization of transistor performance using the multiple integrated tip device.