SBIR Phase II: Low cost, scalable and selective electrochemical metallization process technology

Period of Performance: 02/18/2015 - 08/31/2017


Phase 2 SBIR

Recipient Firm

5388 NW Lianna Way
Portland, OR 97229
Firm POC, Principal Investigator


The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project will be to accelerate the mass-scale adoption of 3D integrated circuits (IC) by decreasing the cost and increasing the scalability of 3D through-silicon vias (TSV) interconnects with electrochemical, low cost and selective metallization technology. After its qualification, 3D TSV selective metallization technology will enable fabrication of high performance 3D microsystems at lower cost by replacing costly damascene interconnect technology with selective electrochemical metallization technology for TSV metal fill, bump and redistribution layer formation. The successful completion of this project would have a significant societal impact by accelerating 3D IC wafer technology adoption into state-of-art high performance digital devices such as next generation of smart phones. This project will also have positive economic impact by creating US semiconductor jobs and maintaining US technology leadership over a wide range of electronic applications and consumer electronic devices. This Small Business Innovation Research (SBIR) Phase II project advances a novel three-dimensional through-silicon vias (TSV) selective metallization technology to fabricate low cost and scalable 3D integrated circuits (IC). Physical and economical limitations for two-dimensional scaling (so called "Moore?s Law") prevent further increase of integration density to improve the performance of IC. These challenges have stimulated the development of 3D TSV technology (so called "More than Moore") in order to increase the speed and bandwidth of the devices as well as to decrease the form factor and power consumption of integrated microsystems. However, the mass adoption of 3D IC is limited by the high cost of 3D TSV interconnects (due to the use of expensive vapor deposition and chemical-mechanical damascene processes) and its poor scalability (due to low conformality of physical and chemical vapor deposited films) to high aspect ratios and smaller via sizes. Proprietary and patented 3D TSV selective metallization technology developed during Phase I project will be further optimized and qualified on production tools to address cost and scalability issues of 3D TSV interconnects. Enabling low cost and scalable 3D ICs will allow heterogeneous systems integration for next generation smart phones and other consumer electronic devices.