Development and Verification Tools/Processes for ASICs and FPGAs

Period of Performance: 09/24/2015 - 12/30/2017


Phase 2 SBIR

Recipient Firm

Edaptive Computing, Inc.
1245 Lyons Road Array
Dayton, OH 45458
Firm POC
Principal Investigator


ABSTRACT:A planned upgrade of the US nuclear arsenal will involve the replacement of aging arming and firing systems with FPGA and ASIC-based electronics. Due to the increased complexity of these electronics, a need exists for highly rigorous design verification that can be performed to assure the safety and reliability of these systems. The ECI solution consists of maintaining a well-documented linkage between requirements and fielded components and assuring the component designs meet the requirements through innovative methods of model checking. In order to check that the design-under-test has matched functionality of a golden reference model based on the original requirements, ECI will continue development of two separate methodologies for checking models adhere to specified requirements. The first of these methodologies is the REVEAL Requirements verification tool which provides a structured framework to link high-level requirements to evidence that supports the fulfillment of those requirements. This evidence is comprised of derived requirements from the high-level requirements, model source code, and model-checking code. The second methodology is verification through formal methods of model checking and examination of the entire state space. This will consist of performing real-time logic checking along with highly structured fault-injection permutations for continued safe operation in adverse conditions.BENEFIT:There is growing need for assured microelectronics as failures in weapon systems could have far-reaching consequences jeopardizing the success of a mission, the welfare of our nation and in the case of a nuclear accident, human life altogether. Microelectronics can experience faults and subsequent failures due to a variety of reasons including poor design, manufacturing deficiencies, and out-of-spec physical conditions. Design strategies and methods need to be improved to not only exhibit correct design functionality, but to also assure that if faults do occur, the system will not enter an unsafe state. Verification process flows will be developed for this effort which will give the Air Force and its Primes a systematic method to screen for failure modes that lead to unsafe states. With REVEAL, failures in manufactured circuits will be traced back to faults that may occur in its functionality, which will save time and money by assuring safe and rugged designs before manufacturing. We envision applications of REVEAL within the DoD, NNSA, and market areas where an utmost level of safety is required from factory machinery, and aviation and automotive electronics.