Onboard Data Processing for Fast Detectors

Period of Performance: 02/17/2015 - 11/16/2015


Phase 1 SBIR

Recipient Firm

Voxtel, Inc.
15985 NW Schendel Ave. Suite 200
Beaverton, OR 97006
Firm POC
Principal Investigator


At modern BES facilities, state-of-the-art detectors generate hundreds to thousands of frames per second, and the resulting data rates are growing faster than network, storage, and analysis capabilities. Current systems are generating tremendous amounts of data, and, in the near future, the implementation of new experimental techniques (e.g., pulse slicing for enhanced time resolution on high-resolution detector arrays) will significantly increase data rates and volumes from existing facilities. As detector format gets larger and mosaics of detector arrays are used, the problem scales. These factors have combined to create a scientific environment in which the pace of discovery may not be limited by experimental constraints, but by the ability of research groups to manage, analyze, and ultimately understand the data resulting from the experiments. To boost computation efficiency and reduce communication latency, heterogeneous components that are currently located far apart can be brought together to enable better computing density at a lower cost and power. When such low-energy heterogeneous control and computing solutions are located close to, or embedded within, the detector layer, local processing and data reduction can reduce the required data bandwidth and the amount of storage, enabling finer temporal and spatial resolution in smaller-sized and lower-cost instruments. However, mass adaptation of heterogeneous computing platforms within tightly integrated detectors, remains elusive for many DOE instruments, mostly due to the challenging task of the software/hardware codesign and the expert-level programming required. Science experiments do not benefit from consumer-segment economies of scale; thus, the cost to develop, maintain, and reconfigure disparate heterogeneous (e.g., multicore/many-core, distributed or hybrid) computing platforms, and to reengineer and parallelize sequential legacy applications, is prohibitive. A reconfigurable processing technology will be developed that tightly integrates heterogeneous processing, control, and reconfigurable processing logic with the detector, allowing massively parallel I/O of detector arrays, with real- time data processing, data communication between adjacent neighboring detector/processor nodes, flexible formatting of data, and real-time visualization. In Phase I, we will demonstrate a small, low-cost (< $100) multichannel heterogeneous detector processing node. We will also demonstrate how, abstracted from the hardware and underlying firmware, we can configure the processing node to perform real-time signal acquisition, filtering, pulse detection, energy discrimination, and time-to-digital conversion (TDC), on a large number of parallel channels, at low power. Open-source software will be developed to allow platform-independent operation. The low-cost digital pulse processor is designed to tightly integrate with detectors and detector arrays, and can be used in any of a variety of applications where the detector array size or number of detector element results in unwieldy data bandwidth and storage requirements. Applications include military imaging, automotive collision avoidance and autonomous navigation, laser radar and 3D imaging, and medical imaging including computed tomography and PET imaging systems. Key Words: Digital signal processing, FPGA, reconfigurable logic, DSP, digital pulse processing, digital waveform processing, image processing, virtualization. Summary for Members of Congress: Todays detectors generate too much data to be readout and transmitted before it is processed. To reduce the amount of data that is transmitted and stored before it is processed, a low cost-reconfigurable computing environment will be developed and made available via open source, which will provide instrument users the ability to implement algorithms, while remaining abstracted from the underlying hardware.