FPGA Acceleration for Simulation & Test EnviRonment (FASTER)

Period of Performance: 01/01/2014 - 12/31/2014


Phase 1 SBIR

Recipient Firm

Colorado Engineering Inc.
1915 Jamboree Drive Array
Colorado Springs, CO 80920
Principal Investigator


CEI along with teammates NVIDIA and Altera wish to propose the following heterogeneous CPU, GPGPU and GPFPGA system with the following six benefits: 1. CEI proposes extending the existing NVIDIA nvcc preprocessor to optimize selection of computing resources based on profiler information generated by the application. 2. CEI would propose exploring Hybrid Memory Cube (HMC) configurations that allow for low latency transfers between GPGPUs and GPFPGAs using the existing GPUDirect infrastructure. 3. CEI hypothesis is that it all performance depends on the application and needs extensive modeling and profiling to understanding. These would be heuristics that could be integrated back into key benefit #1 with nvcc extensions. 4. CEI proposes to extend UCCS and CEI?s work under STTR OSD11-T01 ?Autonomic Performance Assurance (APA) for Multi-Processor Supervisory Control? to include variables for element power consumption. 5. Overall power will be reduce dramatically over CPU/GPGPU based systems by 33% to 66% over CPU/GPGPU systems. 6. In a 4U 19? rack mount chassis, a GPFPGA co-processor system with 160 to 200 TFLOPS system could be realized for only 1600W to 2000W and approximately 100 GFLOPS/W which is 2X to 4X better than the state of the art GPGPU/CPU system. Approved for Public Release 14-MDA-8047 (14 Nov 14)