SBIR Phase I: Low-density parity-check error correction for enhanced reliability of flash memories

Period of Performance: 01/01/2014 - 12/31/2014


Phase 1 SBIR

Recipient Firm

Codelucida, LLC
7479 N Calle Sin Celo
Tucson, AZ 85718
Principal Investigator, Firm POC


The broader/commercial impacts of this this Small Business Innovation Research (SBIR) Phase I project are both technical and economic. The developed error-correction solutions will enable flash-memory-based devices to have higher capacities, higher reliability, and faster speeds at lower power while driving down the cost. This will have a major impact on mobile computing capabilities and enterprise storage by improving the efficiency and reliability of data centers, servers, and mission-critical storage that incorporate flash memories. Improved enterprise storage boosts the efficiency and growth of IT businesses, e-commerce, and financial trade. The solutions will also enable reduced power consumption and heat dissipation leading to greener systems, which is also a key driver for increased economic growth. From 2000 through 2012, the U.S. GDP has increased by 23.12% while energy consumption from all sources has increased by only 3.88% and this trend will be reinforced. The benefits of the error-correction solutions are also applicable to the hard disk drive and communications industries involving hundreds of billions of dollars in revenue and double digit growth rates. This Small Business Innovation Research Phase 1 project is related to the development of novel low-density parity-check (LDPC)-based error-correction for flash memory-based solid state drives (SSDs). While SSDs are rapidly gaining prominence especially in enterprise storage due to their high speeds, low power, and low heat dissipation, they face a major scaling problem as flash memory cell sizes must be shrunk to reduce their high cost, leading to an unavoidable degradation in the reliability. With a trend of increasing die density to enable higher storage capacities, more powerful error-correction is required. Therefore, the industry is swiftly moving towards adopting LDPC codes which can provide greater error-correction than the currently used codes. However, LDPC codes have a high decoding complexity and suffer from the error floor problem which prevents them from achieving very low error-rates needed in storage. Existing LDPC solutions use complex post-processing to deal with the error floor problem at the cost of more power and hardware making them unattractive for next generation SSDs. Using a unique design approach based on the analysis of iterative decoder failures, new LDPC solutions will be developed and validated on hardware that will achieve the target reliability enhancements needed for emerging memories, with a reduction of 10-20% in hardware and power compared to state-of-the art solutions. They will be optimized specifically to meet the reliability needs of enterprise SSD.