SBIR Phase II: Analog/Mixed-Signal Integrated Circuit Verification Coverage

Period of Performance: 01/01/2014 - 12/31/2014


Phase 2 SBIR

Recipient Firm

Zipalog, Inc.
850 Central Parkway East, Suite 160
Plano, TX 75074
Principal Investigator, Firm POC


The broader impact/commercial potential of this project is to increase the competitiveness of U.S. semiconductor industry by improving the quality of A/MS design verification, improving first pass design success and reducing time-to-market. Today, current analog verification methods and tools often fail to catch design mistakes, especially due to unforeseen interactions across chip subsystems, and these mistakes are a frequent cause of costly delays in bringing products to market even on chips where analog is only a small portion of the overall design ? a $63 billion market. The costs and lost profit potential related to multiple design versions can quickly run to millions of dollars and easily dwarfs the cost of providing designers access to the appropriate design tools. Using two different market analyses, the first using a digital verification market analogy and the second considering worldwide new (not slight derivatives) designs in just the AMS IC market, leads to an estimation of total available market for new analog verification solutions of $300 million annual revenue. Further extending the verification solutions with analytics and collaboration tools can potentially increase the market by a further 50% to $450 million annual revenue. Understanding A/MS verification coverage is a key component of this opportunity. This Small Business Innovation Research (SBIR) Phase 2 project proposes a verification coverage system for analog/mixed-signal (A/MS) integrated circuit development. Verification of today?s complex integrated circuits and systems is widely acknowledged as a critical challenge to improving design productivity. Part of the verification challenge revolves around understanding what portion of the operating space has been examined; i.e., ?covered?. Today well-accepted formal and simulation-based techniques exist to capture and measure test coverage for digital integrated circuits, but there is no corresponding commercial capability for analog and mixed-signal integrated circuits. Analog designers frequently spend too much time analyzing and over-testing system behavior for a small set of well understood usage scenarios while leaving significant portions of the state-space completely untested. The design exploration problem for A/MS circuits presents a critical challenge for implementing such systems due to the inherently large design space associated with these types of circuits. Key objectives for the project include productizing and extending key components demonstrated in the Phase 1 prototype. This project will deliver a commercial product to provide A/MS verification coverage data that is actionable and facilitates collaboration between design and verification teams. The resulting product will have scalability and performance to handle large complex designs.