Photodetectors for Optical Signal Processing

Period of Performance: 02/06/1991 - 02/06/1993

$160K

Phase 2 SBIR

Recipient Firm

Tanner Research
34 Lexington Avenue Array
Ewing, NJ 08618
Principal Investigator

Research Topics

Abstract

WE PROPOSE TO INVESTIGATE, DEVELOP, HAVE FABRICATED, TEST, AND DELIVER THREE HIGH-SPEED IMAGING SENSORS BASED ON CUSTOM INTEGRATED CIRCUITS. THE SENSORS WILL PERFORM ANALOG-TO-DIGITAL CONVERSION ON-CHIP TO PRODUCE HIGH-SPEED DIGITAL IMAGE DATA FOR TRANSMISSION OFF-CHIP. THE SENSORS WILL BE AN EXTENSION OF OUR PHASE I EFFORT WHICH PRODUCED A 64 PIXEL SENSOR WITH 5-BIT ANALOG-TO-DIGITAL CONVERSION ON CHIP. WE WILL DELIVER A 256 PIXEL SENSOR WITH EIGHT BIT ON-CHIP CONVERSION EARLY IN PHASE II AND BY THE END OF PHASE II DELIVER A 2048 PIXEL SENSOR WITH 10 TO 12 BITS OF RESOLUTION. EACH OF THESE DEVICES IS TO OPERATE AT 10,000 FRAMES/SECOND. IN ADDITION WE WILL DELIVER A 256x256 PIXEL SENSOR OPERATING AT 400 FRAMES/SECOND WITH A RESOLUTION OF 10 TO 12 BITS. OUR APPROACH WILL UTILIZE STANDARD READILY AVAILABLE CMOS BULK INTEGRATED CIRCUIT TECHNOLOGY SO PRODUCTS ARISING FROM THIS R&D CAN BE FABRICATED RELIABLY AND ECONOMICALLY BY A NUMBER OF VENDORS. THE DEVELOPMENT OF THE PHASE II HIGH-SPEED IMAGE SENSORS WITH INTEGRATED A/D CONVERTERS IS A NATURAL EXTENSION OF OUR PHASE I WORK AND LEADS DIRECTLY TO AN INEXPENSIVE PRODUCT WITH WIDE APPLICABILITY IN COMMERCIAL, ACADEMIC, AND MILITARY MARKETS. A HIGH-SPEED SENSOR WITH DIRECT DIGITAL OUTPUT SIMPLIFIES OPTICAL SIGNAL PROCESSING SYSTEMS IN THE LABORATORY AND IN PRODUCTION. THE REDUCED SIZE, WEIGHT, CHIP COUNT, POWER REQUIRED, AND INCREASED RELIABILITY ARE ESPECIALLY CRITICAL TO HIGH-PERFORMANCE FLIGHT SYSTEMS.