Radiation Hardened Cache Memory

Period of Performance: 07/08/2014 - 03/25/2015


Phase 1 SBIR

Recipient Firm

Scientic, Inc.
6700 Odyssey Drive, Suite 105
Huntsville, AL 35806
Principal Investigator

Research Topics


ABSTRACT: This effort will evaluate radiation hardened cache memory architectures with respect to future device parameter requirements; identify potential Air Force PNT systems, DoD, and commercial aerospace application requirements; select a suitable RH cache architecture to meet anticipated memory size, performance, and radiation requirements; and initiate the design of an advanced RH cache which meets or exceeds the noted radiation hardness levels. Cache memory has been used effectively for years to improve the computation performance of microprocessors. In microprocessors, the processor operations are performed on data contained within the register file via instructions that are loaded from main memory. Cache was implemented as a smaller, faster bridge between the register file and main memory to complement the processor speed. Systems operating in either a natural space or a nuclear weapons system radiation environment need radiation-hardened cache memory to ensure accurate processor functions. Scientic and Sandia National Labs (SNL) propose to leverage the efforts performed by our team in developing SONOS-based NVMs to identify, characterize, and design an advanced state-of-the-art RH cache architecture, tailored to the AF Space application requirements, which can be implemented in existing fabrication processes to reach this goal. Our concept is to build the basic RH cache out of commercially available static random access memory (SRAM) that meets the radiation hardness criteria except for single event upset (SEU), and mitigate the SEUs through the architecture. This will deliver the best cache performance with the least penalty from the radiation hardening. BENEFIT: Systems operating in either a natural space or a nuclear weapons system radiation environment needs radiation-hardened cache memory to ensure accurate processor functions. Potential applications for this device include command and control, navigation, communication, and data processing for interceptors, defense and commercial satellites, and other military and space flight systems. Successful completion of this program will result in a fully qualified, commercially available power efficient, high speed, radiation hardened cache memory device to meet system requirements. Commercialization of this device will involve a proven team consisting of Scientic, SNL, OSU, and NGC (where appropriate). Our team has been successful in developing, fabricating, qualifying, marketing, and selling 64Kb, 256Kb and 1Mb radiation-hardened SONOS-based EEPROM devices for defense and aerospace applications, and is currently developing a 128Mb radiation-hardened SONOS-based EEPROM under a SBIR Phase II contract to the Missile Defense Agency (MDA). Based on our past program history and device development successes, we anticipate supplemental funding to be available to support Phase III efforts. To ensure commercialization success of this program, the architecture and memory design selected in this Phase I effort will be compatible with a typical CMOS fabrication process flow to the greatest extent possible. As noted in Section 1.0, we will assess the SRAM fabrication options available at various trusted commercial processes. However, it is expected that one of the IBM silicon-on-insulator (SOI) processes will be the best suited for this project.