Development and Verification Tools/Processes for ASICs and FPGAs

Period of Performance: 06/20/2014 - 03/02/2015


Phase 1 SBIR

Recipient Firm

Edaptive Computing, Inc.
1245 Lyons Road Array
Dayton, OH 45458
Principal Investigator

Research Topics


ABSTRACT: With a constant push toward improving device robustness and reliability, our proposal is specifically aimed at fulfilling the objectives stated in the solicitation; we will develop and deploy tools, methods, and models for certifying that Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC) meet safety assurance standards. ECI is pioneering innovative solutions to comprehensively specify, rapidly verify/validate, and accurately monitor complex systems and components in military and aerospace applications. As part of these efforts, we have developed significant expertise, building blocks, and capabilities to provide automated electronically assisted inspection through testing and results analysis. The proposed EDAptive® REVEAL solution builds on previous Edaptive Computing, Inc. (ECI) knowledge and technology itself innovative to validate devices against formal requirements definitions. The resulting capabilities will result in a coalescence of multiple verification tools brought together in a complete, user-interactive, graphical based, application for testing devices. We will use the REVEAL platform to map requirements, run simulations, and apply formal machine-based verification to identify design problems and achieve the primary objective of ensuring devices have the greatest quality and margins of safety. BENEFIT: There is growing need for assured microelectronics as failures in weapon systems could have far-reaching consequences jeopardizing the success of a mission, the welfare of our nation and in the case of a nuclear accident, human life altogether. The microelectronics supply chain for defense electronics systems can use parts that come from a large variety of suppliers over a products life cycle, resulting in many opportunities to disrupt critical functions by inserting backdoors and malicious content. Design strategies and methods need to be improved to not only exhibit correct design functionality, but to also assure that only what is designed is implemented and nothing more. Verification process flows will be developed for this effort which will give the Air Force and its Primes a systematic method to screen for malicious alterations and defective components which are prone to fail. After a design has undergone thorough verification, system reliability will be increased and a higher degree of safety will be obtained. With REVEAL, failures in manufactured circuits which have not been completely verified will be precluded, there will be greater assurance that fielded hardware only implements its specified functionality, critical systems will be more easily maintained, and ownership costs will be reduced. We envision applications of REVEAL within the DoD, NSA, homeland security and market areas where an utmost level of safety is required from factory machinery, to commercial aircraft, automobiles or roller coasters.