Efficient Manufacturing of Low Defect Density SiC Substrates using a Novel Defect Capped Planarization Assisted Growth (DC-PAG) Method

Period of Performance: 12/05/2013 - 03/09/2016

$750K

Phase 2 SBIR

Recipient Firm

Sinmat, Inc.
1912 NW 67th Place Array
Gainesville, FL 32653
Principal Investigator

Abstract

ABSTRACT: Silicon carbide based power devices has several advantages because it can be used in very high power, high temperature, high frequency applications, where conventional silicon devices cannot be used. Despite significant advancement in SiC semiconductor technology in the past 3 decades, the presence of device killing defects in the epilayer has impeded the rapid commercialization of SiC-based power devices such as MOSFETs, bipolar-mode diodes and thyristors. Current state of the art methods to reduce these defects have made incremental progress and primarily rely on improvements in conventional growth techniques. A new substrate defect engineering technology has been proposed and demonstrated to reduce defects in SiC epilayers. The reduced defect density epilayers based on the defect engineered substrate will increase the performance SiC devices, device yield and hence can reduce the cost of manufacturing. BENEFIT: The high performance, low cost SiC devices will enable its applications in high power, high frequency and alternative energy applications. Silicon carbide (SiC) power devices can be used in applications such as solar inverters, power conversion in computing and network power supplies, variable-speed drives for industrial motors and hybrid electric vehicles, and products used in high-power, harsh-environment military and aerospace environments.