Development of Digital Receiver/Exciters for Missile Defense Radars

Period of Performance: 03/01/2007 - 08/28/2007


Phase 1 SBIR

Recipient Firm

Applied Radar, Inc.
315 Commerce Park Road, Unit 3
North Kingstown, RI 02852
Principal Investigator


This proposal will address the development of digital receivers and exciters capable of supporting > 1 GHz of instantaneous bandwidth (IBW). The technology will be used in large scalable BMD radar arrays employing a digital waveform generator and digital receiver at the analog input/output of each subarray panel. The receivers/exciters include the necessary up/downconversion and local oscillator circuitry necessary to generate or receive an X-band waveform. Recent developments in > 2 GSPS A/D and D/A chipsets and state-of-the-art FPGA technology allow the real-time processing of wideband (> 1 GHz) radar data, while commercially-available MMIC and PLL chipsets allow the translation of the baseband signals to/from X-band. Several challenges exist in the packaging of the mixed-signal electronics in a manner suitable for a large radar array, routing of the high-speed digital signals both on- and off-board, and cohering of the many receiver/exciter channels across the array. The output of the proposed digital receiver/exciter channels would likely be fed to a wideband digital beamformer array. In Phase I, Applied Radar will design the digital receiver/exciter hardware for a single channel, and develop a multi-channel hardware architecture and packaging approach. In Phase II, the hardware will be fabricated and tested, and integrated with an array such as an MDA SPEAR panel.