High-Performance Arbitrated Logic Processing Topology

Period of Performance: 08/12/2013 - 02/12/2014


Phase 1 SBIR

Recipient Firm

Physical Optics Corp.
1845 West 205th Street Array
Torrance, CA 90501
Principal Investigator


To address the SOCOM need for field-operable computing "bricks", Physical Optics Corporation (POC) proposes to develop High-performance Arbitrated LOgic processing Topology (HARLOT) device. HARLOT is a computing brick housed in a man-portable, ruggedized package designed for field use and offers >16 Terabyte non-volatile memory and >1 TeraFLOPS computational capability while consuming 24 hours operation on a single charge with standard military battery packs). This performance results from innovative future-proofed design based on a scalable modular core architecture, COTS components, state-of-the-art graphics processing units (GPUs), and unique software architecture. Its communication-optimized, thread distribution architecture reduces communication overhead by 33% resulting in faster program execution. Its aggressive dynamic power management scheme reduces power consumption by up to 93% over traditional methods. By design, HARLOT allows external laptop-based system control and access to storage via standard and well-supported interfaces (Ethernet or USB). Closed-loop liquid-based cooling keeps the system cool. In Phase I, POC will develop a system CONOPS and requirements document, perform trade studies, and develop preliminary system, hardware and software architectures and designs. The result will be a design document for SOCOM evaluation. In Phase II, we will fabricate a prototype system based on the Phase I design.