Defect Reductions on Si Substrates for HgCdTe MBE Growth

Period of Performance: 01/29/2013 - 01/29/2015

$1000K

Phase 2 STTR

Recipient Firm

Sivananthan Laboratories, Inc.
590 Territorial Drive, Suite H Array
Bolingbrook, IL 60440
Principal Investigator
Firm POC

Research Institution

University of Illinois, Chicago
809 S Marshfield RM 608
Chicago, IL 60612
Institution POC

Abstract

In Phase I, Sivananthan Laboratories (SL) demonstrated the ability to polish Si(211) wafers, as supplied by a vendor with an already fine polish, to an even better surface smoothness and uniformity. SL also demonstrated the molecular beam epitaxy (MBE) growth of CdTe films with better crystalline quality and uniformity using SL-polished 2 cm x 2 cm Si(211) samples, compared to those grown on the vendor-polished Si(211) samples. In Phase II, we propose to scale up and optimize the chemo-mechanical polishing to deliver 3-inch epi-ready Si(211) substrates, which will require a minimum of pre growth processing on the part of the epilayer grower to produce a quality device layer with an area of 25 cm2. We will demonstrate CdTe and HgCdTe growth on 3-inch epi-ready Si(211) wafers with properties exceeding the current state of the art HgCdTe and CdTe films on Si. Using a variety of advanced nondestructive characterization tools, the surface chemistry associated with chemical polishing agents and etchants will be investigated for further optimization of our successful, proprietary chemical polishing protocols, which were developed during the Phase I program. Focal plane arrays (FPAs) will also be fabricated with HgCdTe grown on CdTe/Si layers and characterized to validate SL s polishing process.