Radiation Hard Monolithic SDRAM to Support DDR2 and DDR3 Architectures

Period of Performance: 01/01/2013 - 12/31/2013

$125K

Phase 1 STTR

Recipient Firm

Space Micro, Inc.
10237 Flanders Court
San Diego, CA 92121
Principal Investigator
Firm POC

Research Institution

Arizona State University
660 South Mil Avenue, Suite 312
Tempe, AZ 85287
Institution POC

Abstract

There is no rad hard SDRAM currently available to support DDR2 and DDR3 applications. Space Micro proposes to build a radiation hardened by design (RHBD) SDRAM memory, using a modified version of our HF-Core Memory Controller to solve all the single event effects issues (SEU, SEFI and multiple bit errors). The RHBD SDRAM will be manufactured on known radiation characterized eDRAM (embedded DRAM) ASIC processes: either TSMC or IBM for a Phase II demonstration. The resulting RH-eDRAM (our name for this device), fabricated on a 130 nm process, provides 128 Mbit of radiation hardened (SEU, SEFI, SEL and TID) memory, while a 90 nm IBM process would result in 512 Mbit of DRAM. The RH-eDRAM solves the space reliability problems with a well-understood set of solutions applied: