Large Area Si Substrates for InP Based Electronics and Optical Device Manufacturing

Period of Performance: 07/28/2004 - 07/27/2006

$500K

Phase 2 STTR

Recipient Firm

SVT Assoc., Inc.
7620 Executive Drive
Eden Prairie, MN 55344
Principal Investigator
Firm POC

Research Institution

Northwestern University
1801 Maple Ave.
Evanston, IL 60201
Institution POC

Abstract

InP-based devices have applications encompassing the entire communication technology including wireless and fiber-optic telecommunications. It is especially suitable for very high frequency (up to 200GHz) operation. Therefore they are increasingly a critical component in all military missions. Their manufacturing costs are high in large part due the high cost of InP substrates, and their much smaller size compared to that of Si. Device throughput per wafer is proportional to the square of wafer diameter, so to gain economy of scale larger wafer size is much more favorable. Furthermore, system performance may benefit from integration of the compound semiconductor devices directly on silicon. We propose a Phase II investigation of high quality InP growth on silicon wafers which, when scaled up, could lead to 300 mm wafers for device fabrication. The robustness of the Si substrate will also lower processing costs. Such Si-based wafer platform could make the manufacturing significantly less expensive, and provide advanced architecture for integration of opto- and micro-electronics to silicon-circuits.