SBIR Phase I: TriStar, An Algebraic High Performance Communications Signal Processor

Period of Performance: 01/01/2010 - 12/31/2010


Phase 1 SBIR

Recipient Firm

THE Athena Group, Inc.
Principal Investigator


This Small Business Innovation Research (SBIR) Phase I project will research and develop an innovative and revolutionary core wireless infrastructure technology. Wireless technologies impact virtually every aspect of life and require a new high performance, low latency, low power infrastructure technology to move to the next level. Today, communications and digital signal processors (DSPs) achieve high performance levels by creating multi-processor designs; as a consequence, these systems can be overly complex, costly, and power consuming. The proposed project utilizes a high-performance communications and DSP processor design; one based on an understanding of computer arithmetic rather than a massive infusion of hardware. The Phase I project will (1) develop a mathematical framework in which physically realizable multiplier-less TriStar filters and transforms having user defined critical frequency or frequencies can be derived, (2) develop a design methodology that can optimize TriStar solutions for speed, power, complexity and/or latency; and (3) quantify and validate the performance and packaging gains using powerful EDA tools. The hardware implementation of the resulting multiplier-free system will achieve superior performance, cost, and power consumption when compared to today?s best wireless solutions.