SBIR Phase I: Image Search Engine using Dynamic Routing Circuits

Period of Performance: 01/01/2007 - 12/31/2007


Phase 1 SBIR

Recipient Firm

IQ Engines, Inc.
Berkeley, CA 94710
Principal Investigator


This Small Business Innovation Research Phase I project aims to develop image search and recognition software inspired by the structure of biological vision systems. There are four main components to the proposed system: A hierarchical dynamical routing circuit, an associative memory, a sparse representation of image content and a scene preprocessor. While there has been previous research focused around each of these areas, this project represents one of the first efforts to combine all of these components into the development of a practical object recognition system. The image search and recognition software will be able to recognize objects regardless of their specific pose in an image and will be designed with hardware implementation criteria in mind. The unique properties of the system, such as utilizing the superposition principle to solve the combinatorial explosion in exhaustive search and its parallel architecture, gives it the potential to be a core engine for myriad search tasks unreachable by conventional means. The rapid proliferation of digital images and videos, the growth of the internet, and continuous improvements in computing have conspired to present an unique and timely opportunity for businesses that create or use visual search and recognition software and hardware. The applications for the technology are significant, ranging from national homeland security, to corporate copyright protection, to vision support for the blind, to personal indexing of digital photos. The system developed as part of this project is general enough to be applied to a wide variety of problems in vision as well as some non-vision problems. As a result, it is broadly suitable as a core engine of an intelligent machine solution for a wide variety of applications. Because its unique design is inspired by the primate visual system, it is expected that additional speed advantages coming from the hierarchical and parallel architecture will be realized in a hardware implementation.