Design Tools for Integrated Asynchronous Electronic Circuits

Period of Performance: 10/03/2002 - 06/10/2003

$99K

Phase 1 SBIR

Recipient Firm

Orora Design Technologies, Inc.
18378 Redmond Fall CIty Road
Redmond, WA 98052
Principal Investigator

Abstract

Asynchronous circuit design has the potential to offer orders of magnitude improvement in speed, power dissipation and EMI over synchronous circuit design. It is especially appealing to military electronics due to its extremely low EMI performance and its suitability as an enabling technology for heterogeneous system integration with high reliability and affordability. However, its real silicon success has been extremely limited due to lack of supporting CAD tools. In this SBIR project, we propose to develop CASTER (CMOS Asynchronous System Timing, Energy and Radiation): a CAD tool for silicon-accurate analysis and optimization of timing, power and EMI of asynchronous circuits. CASTER partitions a transistor-level asynchronous circuit into a graph of transistor-channel-connected blocks (TCCB) communicating through asynchronous handshaking signals. Each TCCB can be modeled in the same way as in a synchronous CMOS circuit, and can be analyzed by using parasitic-aware behavioral modeling from DARPA NeoCAD. We propose to study the feasibility of using CASTER for asynchronous performance metric study and design methodology evaluation. Further, we propose to demonstrate coupled optimization of asynchronous circuit density, speed, power and EMI noise by using CASTER to incorporate physical design and layout parameters, and then use our ARSYN optimizer for architecture exploration. The proposed CAD tools CASTER/ARSYN can reduce the design cycle time for asynchronous circuit design. More importantly, by working directly on the extracted parametric transistor netlist from layout, CASTER/ARSYN can deliver the best silicon performance in terms of density, throughput, power consumption and EMI noise, through simultaneous optimization of asynchronous circuit layouts and architectures. The ultimate goal is to enable the wide use of asynchronous circuit design for achieving faster and more reliable electronic circuits with less power consumption and EMI noise. As the first transistor-level analysis tool for asynchronous circuits, CASTER can be a foundation tool comparable to SPICE for analog circuits and PrimeTime for synchronous digital circuits.