Micro-wave Assisted Oxidative Recovery of Cyanide from the Thlocyanate Conatining Solutions

Period of Performance: 01/01/1999 - 12/31/1999


Phase 1 SBIR

Recipient Firm

4750 Longley Lane #202
Reno, NV 89502


Not Available This phase I proposal addresses fabrication and characterization of nanoscale Si MOSFETs on Si-on-insulator (SOI) wafers. A novel approach based on multiple channel gate arrays is proposed to improve radiation-tolerance against SEU events, and achieve low-threshold voltage operation. At nanoscale (<100 nm) dimensions, multiple gate channels will provide increased current flow as well as redundancy against radiation damage. The proposed gate channels will have sub-micrometer periodicity, and will be in the form of wires, or walls embedded in thermally grown oxide. The transistors can be operated either in partially, or fully-depleted mode by either a suitable choice of channel diameter, or gate metallization process. Gate all round transistors are formed by a directional, sidewall metallization process uniquely applicable to this multiple-channel approach. The gate arrays will be fabricated by using interferometric lithography and reactive ion etching. Channel dimensions will be controlled by conventional Si thermal oxidation. Device contacts will be formed using conventional optical lithography. Transistor response will be evaluated for single and multipl channel gate arrays. A cobalt 60 source at AFRL/Kirtland Air Force Base will be used for radiation treatments.