GENERALIZED DATA COMPRESSION TECHNIQUES FOR TESTABLE DESIGN OF VLSI

Period of Performance: 01/01/1988 - 12/31/1988

$49K

Phase 1 SBIR

Recipient Firm

Compression Telecommunications
2-233 Professional Drive
Gaithersburg, MD 20879
Principal Investigator

Abstract

WITH THE INCREASE IN OUR DEPENDENCE ON COMPUTERS IN ALL PHASES OF OUR LIVES, IT IS BECOMING IMPERATIVE THAT, AS FAR AS POSSIBLE, THE COMPUTERS BE FAULT-TOLERANT, I.E. BE CAPABLE OF PERFORMING IN THE PRESENCE OF FAILURES. ONE CRITICAL ASPECT OF FAULT-TOLERANT COMPUTING IS THE NECESSITYTO DESIGN TESTABLE VLSI CIRCUITS. IN THIS RESEARCH PROPOSAL, A NEW TECHNIQUE FOR BUILT-IN-TEST (BIT) OF VLSI CIRCUITS IS PRESENTED. THE TECHNIQUE IS BASED ON THE GENERALIZED DATA COMPRESSION CONCEPT AND ASSUMES UNDERLYING BUILT-IN-LOGIC-BLOCK- OBSERVABILITY (BILBO) AND LEVEL-SENSITIVE-SCAN-DESIGN (LSSD) STRUCTURES. THE TECHNIQUE ADDRESSES TWO MAIN ASPECTSOF THE TESTABLE DESIGN OF VLSI, NAMELY, I) DESIGN OF REDUCED SIZE TEST PATTERNS THROUGH A NEW DATA COMPRESSION ALGORITHM GENERATED USING A FAULT INFORMATION DATA BASE. II) CIRCUIT MODIFICATION OR AUGMENTATION FOR TESTABILITY I.E. BY PROPER SELECTION OF SUITABLE FINITE STATE MODELS, IMPLEMENTATIONS AS PROGRAMMABLE ARRAYS WITH AND WITHOUT OBSERVABLE OUTPUTS ARE REALIZED. THEN NECESSARY HEURISTICS FOR TESTING ARE GENERATED. THE PROPOSED TECHNIQUE MAY BE USED FOR BIT TEST OF CERTAIN CRUCIAL PARTS OF A COMPUTER, SUCH AS A 'CONTROL UNIT', FOR ENSURING SYSTEM RELIABILITY AND FOR REDUCING THE OVERALL TESTING TIME AND COST.