An Efficient Parallel SAT Solver Exploiting Multi-Core Environments

Period of Performance: 01/01/2009 - 12/31/2009

$100K

Phase 1 SBIR

Recipient Firm

Aries Design Automation, LLC
2705 West Byron Street
Chicago, IL 60618
Principal Investigator

Abstract

The hundreds of stream cores in the latest graphics processors (GPUs), and the possibility to execute non-graphics computations on them, open unprecedented levels of parallelism at a very low cost. We will investigate ways to efficiently exploit this parallelism in order to accelerate the execution of a Boolean Satisfiability (SAT) solver. SAT has a wide range of applications, including formal verification and testing of software and hardware, scheduling and planning, cryptanalysis, and detection of security vulnerabilities and malicious intent. We bring a tremendous expertise in SAT solving, formal verification, and solving of Constraint Satisfaction Problems (CSPs) by efficient translation to SAT. In our previous work (done on the expenses of our company) we obtained 2 orders of magnitude speedup in solving Boolean formulas from formal verification of complex pipelined microprocessors, as well as 4 orders of magnitude speedup in SAT-based solving of CSPs. We expect to achieve speedups of up to 1 ýý 2 orders of magnitude in Phase 1, and up to 3 ýý 4 orders of magnitude in Phase 2.