A Single Event Upset Immune Re-Programmable FPGA Utilizing a Commercial Architecture

Period of Performance: 07/25/2003 - 01/29/2004

$70K

Phase 1 SBIR

Recipient Firm

Structured Materials Industries
201 Circle Drive North Unit # 102
Piscataway, NJ 08854
Principal Investigator

Abstract

Radiation tolerant Field Programmable Gate Arrays (FPGA's) have gained wide and rapid acceptance by military and aerospace equipment suppliers; however, there are presently a limited number of chip-sets available for production. The lack of FPGA alternatives severely limits the range of available functions and applications that would greatly benefit from increased performance with radiation hardness. Further, FPGA technology that can be produced from common mass production techniques is highly sought after for significant cost savings on a per unit basis. We propose to use our newly invented radiation tolerant high temperature non-linear dielectric to develop a Single Event Upset (SEU) immune re-programmable and nonvolatile logic device, a small FPGA, that is immune to SEU events. In Phase I we will show proof of our high temperature non-linear dielectric proof of concept and in Phase II we will optimize the technology for prototype demonstration in a commercial manufacturing environment using common mass production techniques, and demonstrate packaged device functionality for use in radiation environments. Phase III will be product introduction to the military and commercial space markets. A ferroelectric Field Re-Programmable Gate Array has significant potential to replace existing "one time" programmable logic devices with increased functionality in a nonvolatile element. These radiation hardened devices will directly address an annual military market of approximately $250M as well as be applicable to an approximate commercial Programmable Logic Device (PLD) annual market of over $1B.