Peregrine: A High-Precision, High-Speed Analog to Digital Converter

Period of Performance: 06/07/2002 - 03/07/2002


Phase 1 SBIR

Recipient Firm

THE Athena Group, Inc.
Principal Investigator


Mobile wireless communication systems designers face the challenge of increasing the digital content of their solutions. Digital processing begins with the first analog-to-digital converter (ADC), which ideally is as close to the antenna as possible. At present, however, existing ADC technology imposes significant speed, power, and precision implementation barriers. For this reason, the U.S. Air Force has challenged the technical community to develop a high-speed, low power, high-precision ADC. The Air Force requirements include 16-bit resolution, 50 MHz minimum bandwidth, 100 MSPS throughput rate, and a power dissipation of less than 100 mW. The proposer's response to this challenge is a radically new ADC technology called Peregrine. Peregrine differentiates itself from other ADC architectures by virtue of the fact that it is based on a number theoretic approach to ADC conversion. Peregrine data conversion is performed within independent small wordlength channels which reduce the ADC mapping to a collection of concurrent low-complexity operations. The Phase I study will research this new ADC architecture, quantifying speed and power metrics for the 16-bit, or better, CMOS design implementations required in mobile wireless applications such as GPS. When commercialized, the resulting Peregrine ADC will be embedded into high-performance wireless system-on-chip (SoC) solutions. The commercial value of the developed technology is substantial since it will facilitate superior wireless solutions and enable new advanced communication SoC designs. This market, which includes GPS, is enormous. The proposer's experience in developing and licensing solutions as intellectual property (IP) in this arena provides a fast and viable track to commercialization.